Accurate prediction of quality metrics for logic level designstargeted toward lookup-table-based FPGAs

摘要

The importance of efficient area and timing estimation techniquesnis well-established in high-level synthesis (HLS) since it allows morenefficient exploration of the design space while providing HLS tools withnthe capability of predicting the effects of technology-specific tools onnthe design space. Much of the previous work has focused on estimationntechniques that use very simple cost models based solely on the gatenand/or literal count. Those models are not accurate enough to allowneffective design space exploration since the effects of interconnect cannindeed dominate the final design cost. The situation becomes even worsenwhen the design is targeted to field-programmable gate array (FPGA)ntechnologies since the wire delay may contribute up to 60% of thenoverall design delay. In this paper, we present an approach ofnestimating area and timing for lookup-table-based FPGAs that takes intonaccount not only gate area and delay, but also the wiring effects. Wenselect the Xilinx XC4000 series as our main concentration because ofntheir popularity. We tested our estimator with several benchmarks andnthe results show that we receive accurate area and timing estimatesnefficiently