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Asynchronous Protocol Converters for Two-Phase Delay-Insensitive Global Communication

机译:两相时延不敏感全局通信的异步协议转换器

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摘要

As system-level interconnect incurs increasing penalties in latency, round-trip cycle time and power, and as timing-variability becomes an increasing design challenge, there is renewed interest in using two-phase delay-insensitive asynchronous protocols for robust system-level communication. However, in practice, it is extremely inefficient to build local asynchronous computation nodes with two-phase logic, hence four-phase (i.e., return-to-zero) computation blocks are typically used. This paper proposes two new architecture for a family of asynchronous protocol converters that translate between two- and four-phase protocols, thus facilitating robust system design using efficient global two-phase communication and local four-phase computation. A converter circuit is implemented and evaluated a 0.18 micron TSMC process through post-layout simulation, assuming both a small computation block (8 times 8 combinational multiplier) and an empty computation block (FIFO stage).
机译:随着系统级互连对延迟,往返周期时间和功耗的惩罚越来越大,并且随着时序变化成为越来越多的设计挑战,人们对使用两相时延不敏感的异步协议进行健壮的系统级通信有了新的兴趣。但是,实际上,用两相逻辑来构建局部异步计算节点效率极低,因此通常使用四相(即归零)计算块。本文为异步协议转换器系列提出了两种新架构,这些协议可以在两阶段协议和四阶段协议之间转换,从而使用高效的全局两阶段通信和局部四阶段计算促进了鲁棒的系统设计。假设一个小的计算块(8乘8组合乘法器)和一个空的计算块(FIFO级),则通过布局后仿真来实现并评估一个0.18微米TSMC工艺的转换器电路。

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