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首页> 外文期刊>Very Large Scale Integration (VLSI) Systems, IEEE Transactions on >Design of a CMOS Broadband Transimpedance Amplifier With Active Feedback
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Design of a CMOS Broadband Transimpedance Amplifier With Active Feedback

机译:具有有源反馈的CMOS宽带互阻放大器的设计

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In this paper, a novel current-mode transimpedance amplifier (TIA) exploiting the common gate input stage with common source active feedback has been realized in CHRT 0.18 ¿m -1.8 V RFCMOS technology. The proposed active feedback TIA input stage is able to achieve a low input impedance similar to that of the well-known regulated cascode (RGC) topology. The proposed TIA also employs series inductive peaking and capacitive degeneration techniques to enhance the bandwidth and the gain. The measured transimpedance gain is 54.6 dB¿ with a -3 dB bandwidth of about 7 GHz for a total input parasitic capacitance of 0.3 pF. The measured average input referred noise current spectral density is about 17.5 pA/¿{Hz} up to 7 GHz. The measured group delay is within 65 ± 10 ps over the bandwidth of interest. The chip consumes 18.6 mW DC power from a single 1.8 V supply. The mathematical analysis of the proposed TIA is presented together with a detailed noise analysis based on the van der Ziel MOSFET noise model. The effect of the induced gate noise in a broadband TIA is included.
机译:本文在CHRT 0.18μm-1.8 V RFCMOS技术中实现了一种利用公共栅极输入级和公共源有源反馈的新型电流模式跨阻放大器(TIA)。拟议的有源反馈TIA输入级能够实现与众所周知的可调节共源共栅(RGC)拓扑相似的低输入阻抗。拟议的TIA还采用串联电感峰化和电容性退化技术来增强带宽和增益。对于总输入寄生电容为0.3 pF,测得的跨阻增益为54.6 dB×-3 dB带宽约为7 GHz。测得的平均输入参考噪声电流频谱密度约为7 GHz时约为17.5 pA /μs{Hz}。所测得的组延迟在目标带宽上的65±10 ps以内。该芯片从单个1.8 V电源消耗18.6 mW的DC电源。提出了建议的TIA的数学分析以及基于van der Ziel MOSFET噪声模型的详细噪声分析。包括宽带TIA中的感应门噪声的影响。

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