Configurable Input–Output Power Pad for Wafer-Scale Microelectronic Systems

摘要

We describe, in this paper, a new digital input-output power configurable PAD (CPAD) for a wafer-scale-based rapid prototyping platform for electronic systems. This wafer-scale platform includes a reconfigurable wafer-scale circuit that can interconnect any digital components manually deposited on its active alignment-insensitive surface. The whole platform is powered using a massive grid of embedded voltage regulators. Power is fed from the bottom side of the wafer using through silicon vias. The CPAD can be configured to provide CMOS standard voltages of 1.0, 1.5, 1.8, 2.0, 2.5, and 3.3 V using a single 3.3 V power supply. The digital I/O includes transistors sharing and is embedded within the regulation circuit by combining it with a turbo mode that insures high-speed operation. Fast load regulation is achieved with a 5.5-ns response time to a current step load for a maximum current of 110 mA per CPAD. The proposed circuit architecture benefits from a hierarchical arborescence topology where one master stage drives 16 CPADs with a very small quiescent current of 366 nA. The CPAD circuit and the master stage occupy a small area of 0.00847 and 0.00726 ${rm mm}^{2}$, respectively, in CMOS 0.18-$mu{rm m}$ technology.