首页> 外文期刊>Very Large Scale Integration (VLSI) Systems, IEEE Transactions on >An Ultralow Power Multirate FSK Demodulator With Digital-Assisted Calibrated Delay-Line Based Phase Shifter for High-Speed Biomedical Zero-IF Receivers
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An Ultralow Power Multirate FSK Demodulator With Digital-Assisted Calibrated Delay-Line Based Phase Shifter for High-Speed Biomedical Zero-IF Receivers

机译:超低功耗多速率FSK解调器,具有基于数字辅助校准延迟线的移相器,用于高速生物医学零中频接收器

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摘要

An ultralow power (ULP), multirate frequency shift keying (FSK) demodulator applied for high-speed biomedical zero-IF receivers is presented. A digital-assisted calibrated delay-line (DL) based phase shifter is used for realizing multirate and low jitter demodulation under reported highest data rate. All circuits are operated in subthreshold region for achieving ULP consumption. Moreover, the power consumption of the demodulator is relative to the data rate. Therefore, energy consumption per received bit can be optimized according to the applications. Implemented in 0.18 CMOS process, a minimum energy consumption of 11 pJ per received bit and demodulated peak-to-peak jitter of 1.89 ns are achieved under the maximum data rate of 40 Mb/s.
机译:提出了一种适用于高速生物医学零中频接收机的超低功耗(ULP),多速率频移键控(FSK)解调器。基于数字辅助校准延迟线(DL)的移相器用于在报告的最高数据速率下实现多速率和低抖动解调。所有电路都在亚阈值区域内工作,以实现ULP消耗。此外,解调器的功耗与数据速率有关。因此,可以根据应用优化每接收位的能耗。在最大数据速率为40 Mb / s的情况下,以0.18 CMOS工艺实现的每个接收位的最低能耗为11 pJ,解调峰峰值抖动为1.89 ns。

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