首页> 外文期刊>Very Large Scale Integration (VLSI) Systems, IEEE Transactions on >A Scaling-Assisted Signed Integer Comparator for the Balanced Five-Moduli Set RNS ${2^{n}-1, 2^{n}, 2^{n}+ 1, 2^{n+1}- 1, 2^{n-1}- 1}$
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A Scaling-Assisted Signed Integer Comparator for the Balanced Five-Moduli Set RNS ${2^{n}-1, 2^{n}, 2^{n}+ 1, 2^{n+1}- 1, 2^{n-1}- 1}$

机译:平衡五模集合RNS $ {2 ^ {n} -1,2 ^ {n},2 ^ {n} + 1,2 ^ {n + 1}-1,2的缩放辅助有符号整数比较器^ {n-1}-1} $

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摘要

Signed integer comparison occurs prevalently in process control, sorting, address decoding, and conditional branching. Existing algorithms for magnitude comparison in RNS are based either on parity check or partial reverse conversion. With separately designed RNS sign detectors, they can also be used to compare residue representations of signed integers. In this paper, a radically different approach to this problem is proposed for the five-moduli set {2n - 1, 2n, 2n +1, 2n+1 - 1, 2n-1 - 1}. The signs of the operands in comparison, as well as their difference are detected after scaling by a factor of (22n -1)(2n-1 -1). The resulting finite series in the composite modulus channel is further factored into parallel carry-saved additions in the existing mod 2n and mod 2n+1 - 1 modulus channels, thus reducing the sizes of modulo adders from 5n bits to n and n+1 bits. Upon detecting the signs of the operands and their difference, the relation is inference with a small fraction of logic gates. Our synthesis results in 65-nm CMOS technology show that the proposed design is 36.9% smaller, 7.6% faster, and 45.5% more energy efficient than the best Chinese remainder theorem-II-based magnitude comparator and at least 12.9% smaller, 7.3% faster, and 20.8% more energy efficient than the best reverse-conversion-based implementation of signed integer comparator for the same five-moduli set.
机译:有符号整数比较普遍发生在过程控制,排序,地址解码和条件分支中。 RNS中用于幅度比较的现有算法基于奇偶校验或部分反向转换。通过单独设计的RNS符号检测器,它们也可以用于比较带符号整数的残差表示。本文针对五模数集{2 n -1,2 n ,2 n +1,2 n + 1 -1,2 n-1 -1}。比较后的操作数的符号以及它们的差值在按比例缩放(2 2n -1)(2 n-1 -1)后被检测到。复合模数通道中所得的有限级数被进一步分解为现有mod 2n和mod 2 n + 1 -1模数通道中的并行进位保存加法,从而将模加法器的大小从5n减小位到n和n + 1位。在检测到操作数的符号及其差异时,可以通过一小部分逻辑门进行推断。我们在65纳米CMOS技术上的综合结果表明,与基于最佳中国余数定理II的幅值比较器相比,拟议的设计小36.9%,加快7.6%,能源效率高45.5%,而设计小得多,分别小12.9%,7.3%对于相同的五模数集,与有符号整数比较器的最佳基于反向转换的最佳实现方式相比,速度更快,能源效率更高20.8%。

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