A Low-Power Pipelined-SAR ADC Using Boosted Bucket-Brigade Device for Residue Charge Processing

摘要

A low-power pipelined-successive approximation register (SAR) analog-to-digital converter (ADC) using boosted bucket-brigade device (BBD) for residue charge processing is presented. Boosted BBDs have been used as low-power and high-precision residue charge transfers in multistage pipelined ADCs, with drawbacks of large nonlinearity and severe accumulated common-mode (CM) charge error, which requires power-hungry real-time calibration circuits to control the CM level in each stage. When used in a two-stage pipelined-SAR ADC, only one boosted BBD pair is needed and its input signal range is attenuated remarkably by the first-stage SAR. Thus, zero-power power-up correction circuit can be used to stabilize the output CM level, and the nonlinear error of the boosted BBD is negligible. In addition, with top-plate sampling in the first-stage SAR, two reference voltages for the conventional BBD are also eliminated. A proof-of-principle 10-bit two-stage pipelined-SAR ADC is implemented in a 0.18-n$mu text{m}$nCMOS, showing an signal-to-noise-and-distortion ratio/spurious-free dynamic range of 57.1 dB/71.4 dB at 3.1-MHz input, while consuming 1.87 mW at 40 MS/s for a figure of merit of 78.9 fJ/step. The boosted BBD residue circuit consumes only 0.06 mW or 3% of the total power.