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An FPGA-Based 1-GHz, 128×128 Cross-Correlator for Aperture Synthesis Imaging

机译:基于FPGA的1-GHz,128×128互相关器,用于孔径合成成像

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A $128imes128$ cross-correlator for radiometric imaging using interferometric aperture synthesis is presented in this article. It can achieve a landmark performance of 16.384 trillion correlations/s in a single device by calculating cross-correlation between two inputs having 128 channels each, sampled at 1 GHz, which is so far unreported. Passive imaging using interferometric aperture synthesis requires a large number of antennas and wide bandwidth to provide good radiometric sensitivity. The major challenge for realizing an imager using such a technique is the complexity of the correlator. Use of analog technology for large-scale correlation is not feasible, if not impossible. Even the digital correlator requires a very complex data distribution network that must connect every input signal to multiple processing devices while maintaining the same path lengths for equal delays in all the channels. By implementing a massive correlation in a single field-programmable gate array (FPGA), this correlator design provides a way to reduce the complexity by reducing the number of devices needed to achieve the required processing. Processing of high-speed input data is realized in partially parallel datapaths to achieve a bandwidth of 1 GHz. Integrating a large number of correlator channels in a single device is enabled by the hierarchical design approach. It is implemented using Xilinx Kintex UltraScale XCKU115 device. Its functional verification is performed in simulation to check the correctness of the correlation results. Hardware testing is performed using linear-feedback shift registers for on-chip random data generation, and the results are compared with the expected results calculated offline using MATLAB.
机译:本文介绍了使用干涉孔径合成的用于辐射成像的128×128美元互相关器。通过计算每个输入均具有128个通道的两个输入之间的互相关性(在1 GHz采样),它可以在单个设备中实现16.384万亿个相关性/ s的里程碑式性能,迄今为止尚未报道。使用干涉孔径合成的无源成像需要大量天线和宽带宽,才能提供良好的辐射灵敏度。使用这种技术实现成像器的主要挑战是相关器的复杂性。如果不是不可能的话,将模拟技术用于大规模关联是不可行的。甚至数字相关器也需要非常复杂的数据分配网络,该网络必须将每个输入信号连接到多个处理设备,同时保持相同的路径长度,以在所有通道中保持相同的延迟。通过在单个现场可编程门阵列(FPGA)中实现大规模相关,该相关器设计提供了一种通过减少实现所需处理所需的设备数量来降低复杂性的方法。在部分并行数据路径中实现了高速输入数据的处理,以实现1 GHz的带宽。通过分层设计方法,可以在单个设备中集成大量相关器通道。它是使用Xilinx Kintex UltraScale XCKU115器件实现的。它的功能验证是在仿真中执行的,以检查相关结果的正确性。使用线性反馈移位寄存器执行硬件测试以生成片内随机数据,并将结果与​​使用MATLAB离线计算的预期结果进行比较。

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