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A CMOS Majority Logic Gate and its Application to One-Step ML Decodable Codes

机译:CMOS多数逻辑门及其在单步ML可解码代码中的应用

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The majority logic (ML) gate (MLG) is required in fast decoder implementations to protect memories from transient soft errors. In this paper, a novel MLG design is proposed; it consists of a pMOS pull-up network, an nMOS pull-down network, and an inverter. The proposed design is applicable to an arbitrary number of inputs gamma (and operating as a mirror circuit when gamma is odd). The proposed designs are simply requiring a small number of transistors; when simulated, they offer improved metrics such as reduction in delay, area, and power dissipation compared with existing designs found in the technical literature. When the combined power-delay-area product (PDAP) is considered, the advantages of the proposed designs are pronounced. The application of the proposed MLGs to design fast decoders for one-step ML decodable (OS-MLD) codes is also presented; the results show that the proposed MLGs are very efficient circuits for this coding application.
机译:快速解码器实现中需要多数逻辑(ML)门(MLG),以保护存储器免受瞬态软错误的影响。本文提出了一种新颖的MLG设计。它由一个pMOS上拉网络,一个nMOS下拉网络和一个反相器组成。拟议的设计适用于任意数量的输入伽玛(并且在伽玛为奇数时用作镜像电路)。提出的设计仅需要少量的晶体管。当进行仿真时,与技术文献中的现有设计相比,它们提供了改进的指标,例如,减少了延迟,减小了面积并降低了功耗。当考虑组合的功率延迟区域产品(PDAP)时,提出的设计的优点就很明显。还介绍了所提出的MLG在设计单步ML可解码(OS-MLD)码的快速解码器中的应用。结果表明,所提出的MLG对于该编码应用是非常有效的电路。

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