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A High-Flexible Low-Latency Memory-Based FFT Processor for 4G, WLAN, and Future 5G

机译:适用于4G,WLAN和未来5G的高灵活性,低延迟,基于存储器的FFT处理器

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A high-throughput programmable fast Fourier transform (FFT) processor is designed supporting 16- to 4096-point FFTs and 12- to 2400-point discrete Fourier transforms (DFTs) for 4G, wireless local area network, and future 5G. A 16-path data parallel memory-based architecture is selected as a tradeoff between throughput and cost. To implement a hardware-efficient high-speed processor, several improvements are provided. To maximally reuse the hardware resource, a reconfigurable butterfly unit is proposed to support computing including eight radix-2 in parallel, four radix-3/4 in parallel, two radix-5/8 in parallel, and a radix-16 in one clock cycle. Twiddle factor multipliers using different schemes are optimized and compared, wherein modified coordinate rotation digital computer scheme is finally implemented to minimize the hardware cost while supporting both FFTs and DFTs. An optimized conflict-free data access scheme is also proposed to support multiple butterflies at any radices. The processor is designed as a general IP and can be implemented using a processor synthesizer (application-specific instruction-set processor designer). The electronic design automation synthesis result based on a 65-nm technology shows that the processor area is 1.46 mm(2). The processor supports 972 MS/s 4096-point FFT at 250 MHz with a power consumption of 68.64 mW and a signal-to-quantization-noise ratio of 66.1 dB. The proposed processor has better-normalized throughput per area unit than the state-of-the-art available designs.
机译:设计了一种高吞吐量可编程快速傅里叶变换(FFT)处理器,可支持4G,无线局域网和未来5G的16至4096点FFT和12至2400点离散傅里叶变换(DFT)。选择一种基于16路径数据并行存储器的体系结构作为吞吐量和成本之间的折衷方案。为了实现硬件效率高的高速处理器,提供了一些改进。为了最大程度地重用硬件资源,提出了一种可重新配置的蝶形单元以支持包括并行的八个radix-2,并行的四个radix-3 / 4,并行的两个radix-5 / 8和一个时钟的radix-16的计算。周期。优化和比较了使用不同方案的旋转因子乘法器,其中最终实现了改进的坐标旋转数字计算机方案,以最大程度地降低硬件成本,同时支持FFT和DFT。还提出了一种优化的无冲突数据访问方案,以支持任意半径的多个蝶形。该处理器被设计为通用IP,可以使用处理器合成器(专用指令集处理器设计器)来实现。基于65纳米技术的电子设计自动化综合结果显示,处理器面积为1.46 mm(2)。该处理器在250 MHz时支持972 MS / s 4096点FFT,功耗为68.64 mW,信噪比为66.1 dB。与最新的可用设计相比,所提出的处理器具有更好的标准化的单位面积吞吐量。

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