Energy-management techniques, such as dy-namic-power manage-ment, dynamic voltage scaling, and dynamic frequency scaling, have emerged as effective ways to reduce power consumption-a critical requirement in today's embedded-system designs. These schemes reduce power consumption by shutting down idle components or reducing the performance of components to provide just enough performance for a task. These techniques work on both processing elements, such as CPUs, FPGAs, and ASICs, and the communication buses that transfer data between these elements. But unfortunately, these techniques also increase the complexity of test for design validation and debug.
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