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机译:基于绝缘体上硅衬底的新型低比导通电阻双栅极LDMOS,在漂移区具有多个掩埋p层
College of Communication Engineering, Chongqing University, Chongqing 400044, China;
College of Communication Engineering, Chongqing University, Chongqing 400044, China,National Laboratory of Analogue Integrated Circuits, No. 24 Research Institute of China Electronics Technology Group Corporation, Chongqing 400060, China;
College of Communication Engineering, Chongqing University, Chongqing 400044, China;
College of Communication Engineering, Chongqing University, Chongqing 400044, China;
National Laboratory of Analogue Integrated Circuits, No. 24 Research Institute of China Electronics Technology Group Corporation, Chongqing 400060, China;
National Laboratory of Analogue Integrated Circuits, No. 24 Research Institute of China Electronics Technology Group Corporation, Chongqing 400060, China;
College of Communication Engineering, Chongqing University, Chongqing 400044, China;
College of Communication Engineering, Chongqing University, Chongqing 400044, China;
College of Communication Engineering, Chongqing University, Chongqing 400044, China;
College of Communication Engineering, Chongqing University, Chongqing 400044, China;
SOI; Multiple buried p-layers; Specific on-resistance; Breakdown voltage; RESURF;
机译:利用分开的p型栅极和n型漂移区的电荷平衡实现超低比导通电阻LDMOST
机译:具有P / N柱的超低比导通电阻双栅沟槽SOI LDMOS
机译:具有埋入式超结层的超低比导通电阻700V LDMOS
机译:具有可变低k介电埋层和p埋层的部分SOI功率LDMOS
机译:用于低压集成电路应用的双栅CMOS设计和分析,包括绝缘体上硅MOSFET的物理建模。
机译:具有增强的双栅极和部分P埋层的超低比导通电阻横向双扩散金属氧化物半导体晶体管
机译:具有自偏置累积层的超低特定导通电阻高压PLDMO的仿真研究