Yield Analysis for Electrical Circuit Designs: Many Problems and Some Recent Developments in Electronic Engineering

摘要

After the introduction of transistor level circuit simulators in the late 1960s and their widespread adoption in the 1980s, many tasks have been made available in design environments, such corner and MC analyses, automated search techniques for worst -case corners and statistical corners, and circuit optimization. However, the quiver of math techniques is still not empty. Many researchers have demonstrated much higher levels of automation and generality, especially regarding optimization. In addition to these big topics, other little tricks can also help designers. For instance, often a test bench does not run well for all MC points; for example, the simulation stop time has been set too small to observe an event, such as "output voltage ramped up." This leads to a mixed data set: for many points you can extract correct values for t _startup, but for others the data are not available, and we know only that t_startup ≥ t_sim Luckily, this is enough information to create a reliable estimate. The so-called censored MLE is often used in other fields of science and engineering but not yet in circuit design. There is no need to extend the simulation time and rerun the whole MC analysis. Thanks to the maximum likelihood principle, a small censorization will usually degrade the accuracy only very little. For many problems, we see that there is indeed no almost -free lunch because fundamental mathematical limits exist, especially when it comes to complexity. In these cases, math cannot deliver results that go too far beyond common sense. If something is too good to be true, then it is often not true.