A new algorithm for all-digital phase-locked loops (ADPLL) with fast acquisition and large pulling range is presented in this paper. Based on the proposed algorithm, portable cell-based implementations for clock recovery with functions of a frequency synthesizer and on-chip clock generator are completed by standard cell. These modules have been designed and verified on a 0.6-/spl mu/m CMOS process. Test results are summarized as follows: 1) the proposed ADPLL can satisfy full locked bandwidth and fast acquisition within one data transition; 2) the on-chip clock generator can generate any target clock rate f/sub clock/; and 3) the function of nonreturn-to-zero clock recovery has a maximum f/sub clock//4 recovering capability with a locking range of (/spl tau//sub input//spl plusmn//spl tau//sub input//2)) where /spl tau//sub input/ is the input period.
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机译：提出了一种新的全数字锁相环算法（ADPLL），具有快速采集和大拉范围。基于所提出的算法，标准单元完成了具有频率合成器和片上时钟发生器功能的基于便携式单元的时钟恢复实现。这些模块是在0.6- / spl mu / m CMOS工艺上设计和验证的。测试结果总结如下：1）所提出的ADPLL可以在一个数据转换内满足全部锁定带宽和快速采集的要求； 2）片上时钟发生器可以产生任何目标时钟速率f / sub clock /;和3）归零时钟恢复功能具有最大f / sub时钟// 4恢复能力，锁定范围为（/ spl tau // sub输入// spl plusmn // spl tau // sub输入// 2）），其中/ spl tau // sub input /是输入时间段。
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