An all-digital phase-locked loop (ADPLL)-based clock recoverycircuit

摘要

A new algorithm for all-digital phase-locked loops (ADPLL) withnfast acquisition and large pulling range is presented in this paper.nBased on the proposed algorithm, portable cell-based implementations fornclock recovery with functions of a frequency synthesizer and on-chipnclock generator are completed by standard cell. These modules have beenndesigned and verified on a 0.6-Μm CMOS process. Test results arensummarized as follows: 1) the proposed ADPLL can satisfy full lockednbandwidth and fast acquisition within one data transition; 2) thenon-chip clock generator can generate any target clock rate fclockn; and 3) the function of nonreturn-to-zero clock recovery has anmaximum fclock/4 recovering capability with a locking rangenof (Τinput±Τinput/2)) where Τninput is the input period