SPICE modeling and quick estimation of MOSFET mismatch based onBSIM3 model and parametric tests

摘要

This paper reports a MOS transistor mismatch model applicable fornsubmicron CMOS technologies and developed based on the industry standardnBSLM3v3 model. A simple and unified expression was derived to formulatenthe effect of MOSFET mismatch on drain current variance. A way tonquickly estimate the drain current mismatch was also suggested. Thenmodel has been integrated into HSPICE, and results obtained fromnsimulation and measurements were compared