A multiple-crystal interface PLL with VCO realignment to reduce phase noise

摘要

An enhancement to a conventional integer-N phase-locked loop (PLL) is introduced, analyzed, and demonstrated experimentally to significantly reduce voltage-controlled oscillator (VCO) phase noise. The enhancement, which involves periodically injection locking the VCO to a buffered version of the reference, has the effect of widening the PLL bandwidth and reducing the overall phase noise. It is demonstrated in a 3-V 6.8-mW CMOS reference PLL with a ring VCO capable of converting most of the popular crystal reference frequencies to a 96-MHz RF PLL reference and baseband clock for a direct conversion Bluetooth wireless LAN. The peak in-band phase noise at an offset of 20 kHz is -102 dBc/Hz with the technique enabled and -92 dBc/Hz with the technique disabled. A theoretical analysis is presented and shown to be in close agreement with the measured results.