A 56-mW 23-mm{sup}2 Single-Chip 180-nm CMOS GPS Receiver With 27.2-mW 4.1-mm{sup}2 Radio

摘要

A 56-mW 23-mm{sup}2 GPS receiver with CPU-DSP-64 kRAM-256 kROM and a 27.2-mW 4.1-mm{sup}2 radio has been integrated in a 180-nm CMOS process. The SoC GPS receiver, connected to an active antenna, provides latitude, longitude, height with 3-m rms precision with no need of external host processor in a [-40, 105]℃ temperature range. The radio draws 17 mA from a 1.6-1.8-V voltagfLsupply, takes 11 pins of a VFQFPN68 package, and needs just a few passives for input match and a crystal for the reference oscillator. Measured radio performances are NF = 4.8 dB, Gp = 92 dB, image rejection > 30 dB, -112 dBc/Hz phase noise @ 1 MHz offset from carrier. Though GPS radio linearity and ruggedness have been made compatible with the co-existence of a microprocessor, radio silicon area and power consumption is comparable to state-of-the-art stand-alone GPS radio. The one reported here is the first ever single-chip GPS receiver requiring no external host to achieve satellite tracking and position fix with a total die area of 23 mm{sup}2 and 56-mW power consumption.