A Low-Cost and Low-Power CMOS Receiver Front-End for MB-OFDM Ultra-Wideband Systems

摘要

A full-rate multiplexer (MUX) with a multiphase clock architecture for over 40 Gbit/s optical communication systems is presented. The 4:1 MUX is comprised of a re-timer based on a D-type flip-flop (DFF) and a clock tree system that uses EXOR-type delay buffers to match its skews well to those of the data. The supply voltage is reduced to -1.5 V by analyzing the voltage allocation. Fabricated in a 0.13-mum InP HEMT technology, a DFF test circuit achieved 75-Gbit/s operation and exhibited performance sufficient to re-time 50-Gbit/s serialized data. The 4:1 MUX measurement results demonstrate successful 50-Gbit/s operation at room temperature, and 40-Gbit/s operation, which has 10-11 error free for 231 - 1 pseudorandom bit stream (PRBS) data, up to an ambient temperature of 90 degrees or down to - 1.24 V of supply voltage. The circuit consumes 450 mW at a - 1.5-V supply and exhibits an output jitter of 283 fs rms at 50-Gbit/s operation. We also propose a multiphase clock generator for a MUX that has a serialization of more than four channels