A 40-Gb/s Transimpedance Amplifier in 0.18-$mu$m CMOS Technology

摘要

A 40-Gb/s transimpedance amplifier (TIA) is realized in 0.18-$mu{hbox {m}}$ CMOS technology. From the measured S-parameters, a transimpedance gain of 51 ${hbox {dB}}Omega$ and a 3-dB bandwidth up to 30.5 GHz were observed. A bandwidth enhancement technique, $pi$-type inductor peaking (PIP), is proposed to achieve a bandwidth enhancement ratio (BWER) of 3.31. In addition, the PIP topology used at the input stage decreases the noise current as the operation frequency increases. Under a 1.8 V supply voltage, the TIA consumes 60.1 mW with a chip area of $hbox{1.17}times hbox{0.46} {hbox {mm}}^{2}$. The proposed CMOS TIA presents a gain–bandwidth product per DC power figure of merit $({rm GBP}/P_{rm dc})$ of 180.1 ${hbox{GHz}}Omega/{hbox{mW}}$.