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A Low-Area and Fully Nonlinear 10-Bit Column Driver With Low-Voltage DAC and Switched-Capacitor Amplifier for Active-Matrix Displays

机译:具有低压DAC和用于主动矩阵显示器的低压DAC和开关电容放大器的低频和完全非线性10位列驱动器

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摘要

To reduce the circuit area and support a 10-bit fully nonlinear gamma correction, a new column driver architecture constructed with a 10-bit one-stage low-voltage resistor string digital-to-analog converter (RDAC) (LVDAC) and a switched-capacitor amplifier (SC-AMP) is proposed. Because the LVDAC is implemented with low-voltage (LV) MOSFETs instead of high-voltage (HV) MOSFETs, the circuit area is drastically reduced. In addition, there is no need to use level shifters that must be used in the traditional column driver between the LV logic circuit and the HV DAC, thus further decreasing the circuit area. By utilizing a one-stage DAC architecture, the effective bit resolution of nonlinear gamma correction can be increased compared with previous two-stage DACs, in which the output voltages of the coarse DAC are interpolated. The output voltage of LVDAC is amplified by SC-AMP to reach the requisite HV to drive the display panel. In designing the SC-AMP, the effects of non-idealities, such as random offset voltage, capacitance mismatch, parasitic capacitance, and switching error are quantitatively analyzed, and circuit techniques to suppress the effects are presented. The proposed column driver was fabricated using a 90-nm CMOS process. The circuit area of the proposed 10-bit column driver is only 69.0% of that of the conventional 8-bit column driver because the conventional 8-bit HV RDAC (HVDAC) using 5-V MOSFETs is replaced by the proposed 10-bit LVDAC using 1.2-V MOSFETs, along with the SC-AMP with a gain of four to support the 5-V output voltage range. The measurement results show that the differential nonlinearity (DNL) and integral nonlinearity (INL) are +0.2/-0.18 and +0.42/-0.06 LSB, respectively, with an LSB voltage of 4.5 mV. The measured maximum deviation of voltage outputs (DVOs) between 50 channels is 7.9 mV.
机译:为了减少电路区域并支持10位完全非线性伽马校正,采用10位单级低压电阻串(RDAC)(LVDAC)和交换机构造的新列驱动器架构。 - 提出了一种电容器放大器(SC-AMP)。因为LVDAC以低压(LV)MOSFET实现而不是高压(HV)MOSFET,因此电路区域大大降低。此外,不需要使用必须在LV逻辑电路和HV DAC之间的传统列驱动器中使用的电平移位器,从而进一步降低电路区域。通过利用单级DAC架构,与先前的两级DAC相比,可以增加非线性伽马校正的有效位分辨率,其中粗DAC的输出电压是内插的。 LVDAC的输出电压通过SC-AMP放大,以达到必要的HV以驱动显示面板。在设计SC-AMP时,定量地分析了非理想,例如随机偏移电压,电容失配,寄生电容和切换误差的影响,并且呈现了抑制效果的电路技术。使用90-nm CMOS工艺制造所提出的柱驱动器。所提出的10位列驱动器的电路面积只有69.0%的传统8位列驾驶员,因为使用5-V MOSFET的传统8位HV RDAC(HVDAC)被提出的10位LVDAC取代使用1.2-V MOSFET,以及SC-AMP,增益为四个以支持5V输出电压范围。测量结果表明,差分非线性(DNL)和整体非线性(INL)分别为+ 0.2 / -0.18和+ 0.42 / -0.06LSB,LSB电压为4.5 mV。 50通道之间的电压输出(DVOS)的测量最大偏差为7.9 mV。

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