A 1500 fps Highly Sensitive 256 256 CMOS Imaging Sensor With In-Pixel Calibration

摘要

High-speed CMOS imaging sensors (CIS) normally have low sensitivity because of the large integration capacitance. They also have high noise because pixel circuits cannot implement correlated double sampling (CDS) to remove the pixel reset noise. For applications, such as micro-computed tomography (micro-CT), this is a major limitation. In this work, we developed a technique to achieve high sensitivity and low noise for high-speed CIS. To maximize the sensitivity, we designed a new capacitive transimpedance amplifier (CTIA) pixel with a tiny metal–oxide–metal capacitor. The pixel circuit also implements CDS. As a result, the temporal noise is greatly reduced, and the sensitivity improves dramatically. To compensate the mismatch of small integration capacitors across the pixel array, an on-chip calibration scheme with in-pixel circuits is developed. Fully differential column circuits are designed to suppress the power supply injection in the large array of high-speed column circuits. A successive-approximation analog-to-digital (SAR ADC) is designed to achieve 10-bit resolution and to fit in the 15- $mu{hbox {m}}$ column pitch. For testing modes, column circuits are configured into a two-step ADC to provide 13-bit dynamic range. The 256$,times,$ 256 CIS design is fabricated in a 0.18- $mu{hbox {m}}$ CMOS process. The imager samples up to 1500 fps. The pixel integration capacitor is 0.7 fF, which enables $hbox{68.5~V/lux}cdot hbox{s}$ sensitivity under the white illumination. The CIS temporal noise is $13.6{rm e}^{-}$ . This sensitivity and noise performances are much better than previous high-speed CIS benchmark des- gns. Running at 1500 fps, the CIS can capture recognizable images with illumination down to 1 lux. The on-chip calibration suppresses the fixed-pattern noise lower than 0.52%. The prototype chip consumes 390 mW of power.