An Ultra-Low-Jitter, mmW-Band Frequency Synthesizer Based on Digital Subsampling PLL Using Optimally Spaced Voltage Comparators

摘要

This article presents a cascaded architecture of a frequency synthesizer to generate ultra-low-jitter output signals in a millimeter-wave (mmW) frequency band from 28 to 31 GHz. The mmW-band injection-locked frequency multiplier (ILFM) placed at the second stage has a wide bandwidth so that the performance of the jitter of this frequency synthesizer is determined by the GHz-band, digital subsampling phase-locked loop (SSPLL) at the first stage. To suppress the quantization noise of the digital SSPLL while using a small amount of power, the optimally spaced voltage comparators (OSVCs) are presented as a voltage quantizer. This article was designed and fabricated using 65-nm CMOS technology. In measurements, this prototype frequency synthesizer generated output signals in the range of 28-31 GHz, with an rms jitter of less than 80 fs and an integrated phase noise (IPN) of less than -40 dBc. The active silicon area was 0.32 mm(2), and the total power consumption was 41.8 mW.