Low src='/images/tex/31311.gif' alt='{rm VDDmin}'> Swing-Sample-and-Couple Sense Amplifier and Energy-Efficient Self-Boost-Write-Termination Scheme for Embedded ReRAM Macros Against Resistance and Switch-Time Variations

摘要

The designs of resistive RAM (ReRAM) macros are limited by 1) a small sensing margin, limited read-, and slow read access time () caused by a high cell-resistance and small cell-resistance-ratio (R-ratio) and 2) poor power integrity and increased energy waste attributable to a large SET dc-current () resulting from the wide distribution of write (SET)-times (). This study proposes a swing-sample-and-couple (SSC) voltage-mode sense amplifier (VSA) to enable an approximately greater sensing margin for lower and a faster read speed across a wide range, compared with conventional VSAs. A 4T self-boost-write-termination (SBWT) scheme is proposed to cut off the of devices with a rapid . The SBWT scheme reduces of the with an area penalty below 0.5%. A fabricated 512 row 28 nm 1 Mb ReRAM macro achieved when and confirmed the