机译:统一的基于时钟和开关电容器的供电架构,可实现低压SoC域中的变化容差
Univ Washington, Dept Elect & Comp Engn, Seattle, WA 98195 USA;
Univ Washington, Dept Elect & Comp Engn, Seattle, WA 98195 USA;
Univ Washington, Dept Elect & Comp Engn, Seattle, WA 98195 USA;
Univ Washington, Dept Elect & Comp Engn, Seattle, WA 98195 USA;
Univ Washington, Dept Elect & Comp Engn, Seattle, WA 98195 USA;
Univ Washington, Dept Elect & Comp Engn, Seattle, WA 98195 USA;
Qualcomm Technol Inc, Raleigh, NC 27617 USA;
Univ Washington, Dept Elect & Comp Engn, Seattle, WA 98195 USA;
Near-subthreshold system; phase-locked loop (PLL); process; voltage; and temperature (PVT) variation; supply droop; switched capacitor (SC); UniCaP; voltage margin; voltage regulation;
机译:基于统一的时钟和基于开关电容的电力输送架构,用于低压SoC域中的变化公差
机译:使用统一验证平台的V2.0 + EDR蓝牙的低功耗SOC架构
机译:使用统一验证平台的V2.0 + EDR蓝牙的低功耗SOC架构
机译:使用虚拟分而治之的多时钟域SoC的低功耗,低成本扫描测试架构
机译:具有多个时钟域的SoC的模块间接口技术,可应对现代深亚微米技术中的挑战。
机译:模块化设计应用程序体系结构以及自助服务模型用于企业数据交付的用途:Duke Enterprise Data Unified Content Explorer(DEDUCE)
机译:功率约束下多时钟域SoC的测试调度