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A Low Power SOC Architecture for the V2.0+EDR Bluetooth Using a Unified Verification Platform

机译:使用统一验证平台的V2.0 + EDR蓝牙的低功耗SOC架构

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This paper presents a low-power System on Chip (SOC) architecture for the v2.0+EDR (Enhanced Data Rate) Bluetooth and its applications. Our design includes a link controller, modem, RF transceiver, Sub-Band Codec (SBC), Expanded Instruction Set Computer (ESIC) processor, and peripherals. To decrease power consumption of the proposed SOC, we reduce data transfer using a dual-port memory, including a power management unit, and a clock gated approach. We also address some of issues and benefits of reusable and unified environment on a centralized data structure and SOC verification platform. This includes flexibility in meeting the final requirements using technology-independent tools wherever possible in various processes and for projects. The other aims of this work are to minimize design efforts by avoiding the same work done twice by different people and to reuse the similar environment and platform for different projects. This chip occupies a die size of 30mm~2 in 0.18μm CMOS, and the worst-case current of the total chip is 54 mA.
机译:本文提出了一种用于v2.0 + EDR(增强数据速率)蓝牙的低功耗片上系统(SOC)架构及其应用。我们的设计包括链接控制器,调制解调器,RF收发器,子带编解码器(SBC),扩展指令集计算机(ESIC)处理器和外围设备。为了减少所建议的SOC的功耗,我们使用双端口存储器(包括电源管理单元和时钟门控方法)来减少数据传输。我们还将在集中式数据结构和SOC验证平台上解决可重用和统一环境的一些问题和好处。这包括在各种过程和项目中尽可能使用与技术无关的工具来满足最终要求的灵活性。这项工作的另一个目的是通过避免不同的人进行两次相同的工作来最大程度地减少设计工作,并为不同的项目重用相似的环境和平台。该芯片在0.18μmCMOS中的芯片尺寸为30mm〜2,最坏情况下的电流为54 mA。

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