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Frequency-Hopped Quadrature Frequency Synthesizer in 0.13-$mu$m Technology

机译:采用0.13- $ mu $ m技术的跳频正交频率合成器

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This paper presents a Wireless-USB/WiMedia-compliant fast-hopping frequency synthesizer architecture with quadrature outputs based on sub-harmonic injection-locking. The synthesizer features a cross-coupled quadrature digitally-controlled oscillator, that is injection-locked to a sub-harmonic frequency. An intuitive closed-form expression for the dynamics of the quadrature injection-locked oscillator and a technique to achieve fast frequency-hopping, are presented. The overall architecture, based on this technique, is a CMOS-only implementation and has been fabricated in a 0.13-$mu$ m SiGe BiCMOS process. On-chip mixers have been implemented to measure the quadrature accuracy of the outputs. Measurement results indicate lock-times of less than 2.5 ns, a locked phase noise of ${-}$114 dBc/Hz at 1 MHz offset and a quadrature accuracy of better than 0.5$^{circ}$ . The frequency synthesizer (excluding output buffers) occupies an area of 0.27 mm$^2$ and consumes 14.5 mW of power. The best and worst case spur suppression achieved are 47 and 31 dB, respectively. This is the lowest power fast-hopping quadrature frequency synthesizer that has been reported to date.
机译:本文提出了一种基于Wireless-USB / WiMedia的快速跳频频率合成器架构,该架构具有基于次谐波注入锁定的正交输出。该合成器具有交叉耦合的正交数字控制振荡器,该振荡器被注入锁定至次谐波频率。提出了一种用于正交注入锁定振荡器动力学的直观闭合形式表达式,以及一种实现快速跳频的技术。基于此技术的总体体系结构是仅CMOS的实现,并以0.13- $ mu $ 制成m SiGe BiCMOS工艺。片上混频器已实现以测量输出的正交精度。测量结果表明,锁定时间小于2.5 ns,锁定相位噪声为 $ {-} $ 114 dBc / Hz偏移为1 MHz时,正交精度优于0.5 $ ^ {circ} $ 。频率合成器(不包括输出缓冲区)占用0.27 mm的面积,消耗的功率为14.5 mW。最佳和最坏情况的杂散抑制分别为47 dB和31 dB。这是迄今为止已报道的最低功耗的快速跳频正交频率合成器。

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