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Model Checking Software with First Order Logic Specifications Using AIG Solvers

机译:使用AIG解算器的一阶逻辑规范的模型检查软件

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Static verification techniques leverage Boolean formula satisfiability solvers such as SAT and SMT solvers that operate on conjunctive normal form and first order logic formulae, respectively, to validate programs. They force bounds on variable ranges and execution time and translate the program and its specifications into a Boolean formula. They are limited to programs of relatively low complexity for the following reasons. (1) A small increase in the bounds can cause a large increase in the size of the translated formula. (2) Boolean satisfiability solvers are restricted to using optimizations that apply at the level of the formula. Finally, (3) the Boolean formulae often need to be regenerated with higher bounds to ensure the correctness of the translation. We present a method that uses And-Inverter-Graph (AIG) sequential circuits, and AIG synthesis and verification frameworks to validate programs. An AIG is a Boolean formula with memory elements, logically complete negated conjunction gates, and a hierarchical structure. Encoding the validation problem of a program as an AIG (1) typically provides a more succinct representation than a Boolean formulae encoding with no memory elements, (2) preserves the high-level structure of the program, and (3) enables the use of a number of powerful automated analysis techniques that have no counterparts for other Boolean formulae such as CNF. Our method takes an imperative program with a first order logic specification consisting of a precondition and a postcondition pair, and a bound on the program variable ranges, and produces an AIG with a designated output that is when the program violates the specification. Our method uses AIG synthesis reduction techniques to reduce the AIG, and then uses AIG verification techniques to check the satisfi- bility of the designated output. The results show that our method can validate designs that are not possible with other state of the art techniques, and with bounds that are an order of magnitude larger.
机译:静态验证技术利用布尔公式可满足性求解器(例如SAT和SMT求解器)分别对合态范式和一阶逻辑公式进行操作来验证程序。它们强制变量范围和执行时间的界限,并将程序及其规范转换为布尔公式。由于以下原因,它们仅限于复杂度较低的程序。 (1)范围的小幅增加可能会导致翻译后的公式的大小大幅增加。 (2)布尔可满足性求解器仅限于使用适用于公式级别的优化。最后,(3)布尔公式通常需要以更高的边界重新生成,以确保翻译的正确性。我们提出了一种使用与反相器(AIG)时序电路以及AIG综合和验证框架来验证程序的方法。 AIG是一个布尔公式,具有存储元素,逻辑上完全否定的合取门和分层结构。将程序的验证问题编码为AIG(1)通常提供比没有存储元素的布尔公式编码更简洁的表示形式;(2)保留程序的高级结构;(3)允许使用许多强大的自动化分析技术,这些技术都无法与其他布尔公式(例如CNF)相对应。我们的方法采用具有由前置条件和后置条件对组成的一阶逻辑规范以及程序变量范围上的界限的命令式程序,并生成具有指定输出(即程序违反规范)的AIG。我们的方法使用AIG合成减少技术来减少AIG,然后使用AIG验证技术来检查指定输出的可满足性。结果表明,我们的方法可以验证其他现有技术无法实现的设计,并且边界要大一个数量级。

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