机译:使用外延沟道和堆叠式硅绝缘体结构改善了垂直MOSFET性能
School of Electronics and Computer Science, University of Southampton, Southampton, SO 17 1B J, UK,Department of Electronics and Intelligent Systems, Tohoku Institute of Technology, Sendai, 982-8577,Japan;
School of Electronics and Computer Science, University of Southampton, Southampton, SO 17 1B J, UK,Cavendish Laboratory, University of Cambridge, Cambridge CB3 OHE, UK;
Department of Electrical Engineering and Electronics, University of Liverpool, Liverpool, L69 3GJ, UK;
Department of Electrical Engineering and Electronics, University of Liverpool, Liverpool, L69 3GJ, UK;
Department of Electrical Engineering and Electronics, University of Liverpool, Liverpool, L69 3GJ, UK;
School of Electronics and Computer Science, University of Southampton, Southampton, SO 17 1B J, UK;
机译:二维(2D)分析建模和改进的分级通道栅极堆叠(GCGS)双材料双栅极(DMDG)MOSFET的简短信道性能
机译:具有梯度沟道掺杂的垂直nMOSFET改善了热载流子和短沟道性能
机译:分离两层垂直堆叠SOI纳米线MOSFET的沟道传导的方法
机译:4H-SiC垂直MOSFET中的超低R / sub ons /:掩埋沟道双外延MOSFET
机译:具有低接触电阻和改进的栅极控制的晶片尺度制造和表征凹槽PTSE2 MOSFET
机译:具有纳米堆叠的高k栅极电介质和3D鳍形结构的高性能III-V MOSFET
机译:利用沟道工程技术优化60 nm沟道长度的垂直MOSFET的性能