Modification of a carbon nanotube FET compact model for digital circuit simulation

摘要

Carbon nanotube field-effect transistor (CNTFET) based circuit systems have received extensive attention due to their energy-efficiency benefits. However, there is not yet a generally accepted compact SPICE model for CNTFETs compatible with existing electronics design automation platforms. In this paper, the Stanford top gate CNTFET model is optimized through the consideration of different doping levels in source/drain as well as the simplification of an equivalent capacitance network in the intrinsic channel. Based on this, compact models are built for both top gate and wrapped gate CNTFETs. Then the DC properties and the cut-off frequency of top gate and wrapped gate CNTFETs with 15 nm channel length, and their basic logic circuits based on our modelling, are simulated by HSPICE. In the circuit simulation, we add the influence of gate-to-gate capacitance. The influences of structural parameters such as the diameter, number of CNTs and their gap on the current-voltage property, transconductance, cut-off frequency, circuit delay and power consumption are studied. Through comparison with the simulation using the Stanford model, our modelling is more suitable for the design and development of CNTFET circuits. For given parameters, the top gate CNTFETs have a larger maximum cut-off frequency and the wrapped gate CNTFETs' saturate current is larger. Wrapped gate logic circuits have less delay but more dynamic power than top gate circuits. More CNTs in FETs with a bigger gap and shorter tube pitch lead to less circuit delay and more dynamic power.