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Impact of core thickness and gate misalignment on rectangular core-shell based double gate junctionless field effect transistor

机译:核心厚度和栅极失准对基于矩形核壳的双栅极无结场效应晶体管的影响

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A rectangular core is inserted in double gate junctionless transistor (DGJLT) which separates the top shell and bottom shell in the device called as rectangular core-shell double gate junctionless transistor (RCS-DGJLT). The core doping and core thickness are optimized to improve the performance of RCS-DGJLT. The core thickness is optimized for different shell thicknesses in the device which has not been explored yet in the literature. An interesting observation is found that the core thickness should be equal to the shell thickness for smaller shell thicknesses, whereas the thicker core is required for larger shell thicknesses. RCS-DGJLT has shown remarkable improvement than DGJLT. Further, the effect of gate misalignment on either side (source/drain) of the channel in RCS-DGJLT and DGJLT is studied and compared on the basis of device performance. The study of gate misalignment becomes essential due to the complications on achieving perfectly aligned gates during the fabrication of double gate device. An RCS-DGJLT is found to have better tolerance to gate misalignment than DGJLT. The best parametric values like OFF current is similar to 10(-16)A, ON current is similar to 10(-5)A, subthreshold slope is nearly 66.2 mV/decade, ON/OFF current ratio is similar to 10(10), drain induced barrier lowering is similar to 42.1 mV V-1 and threshold voltage similar to 0.56 V at perfectly aligned gate condition is obtained on keeping core and shell thickness at 3 nm each. As per the analysis, the gate misalignment up to 20% on either side of the channel does not impact the performance parameters much and hence reduces the stress of meeting the requirement of perfect gate alignment.
机译:将矩形芯插入双栅极无结晶体管(DGJLT)中,该器件将器件的顶部外壳和底部外壳分开,称为矩形芯-壳双栅极无结晶体管(RCS-DGJLT)。优化了磁芯掺杂和磁芯厚度,以提高RCS-DGJLT的性能。针对装置中不同的外壳厚度,对芯厚度进行了优化,这在文献中尚未探讨。有趣的发现是,对于较小的壳体厚度,芯厚度应等于壳体厚度,而对于较大的壳体厚度,则需要较厚的芯。 RCS-DGJLT已显示出比DGJLT显着的改进。此外,在器件性能的基础上,研究并比较了栅极失准对RCS-DGJLT和DGJLT中通道的任一侧(源极/漏极)的影响。由于在双栅极器件的制造过程中实现完美对准的栅极的复杂性,栅极失准的研究变得至关重要。发现RCS-DGJLT比DGJLT具有更好的对门不对准的容忍度。最佳参数值,例如OFF电流类似于10(-16)A,ON电流类似于10(-5)A,亚阈值斜率接近66.2 mV /十倍,ON / OFF电流比类似于10(10) ,漏极诱导的势垒降低类似于42.1 mV V-1,并且在将栅极和壳的厚度分别保持在3 n​​m的情况下,在完全对准的栅极条件下获得的阈值电压类似于0.56V。根据分析,通道两侧高达20%的栅极未对准不会对性能参数产生太大影响,因此可降低满足完美栅极对准要求的压力。

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