Device design guideline for junctionless gate-all-around nanowire negative- capacitance FET with HfO_2-based ferroelectric gate stack

摘要

In this study, the electrical characteristics of negative-capacitance junctionless nanowire FETs (NC-JL-NWFET) with an HfO2-based ferroelectric layer are investigated through 3D Sentaurus TCAD and MATLAB simulations. The performances of NC-JL-NWFETs with various aspect ratios (ARs) (i.e., the ratio of horizontal radius to vertical radius), doping concentrations (N), thicknesses of ferroelectric layers (T-fe), and different ferroelectric materials, are studied. The NC-JL NWFETs show improved performances over a broad range of the parameters, compared with the baseline JL-NW-FETs, in terms of subthreshold slope (SS) and on/off drain current ratio (I-on/I-off). Additionally, the impacts of the mentioned parameters on the negative-capacitance effect are presented in terms of the internal voltage (V-int). The optimal parameters with NC-JL is compared to NWFETs with doping junction (J-NW), and then, showed better performance for low power device applications.