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Porous Low-k Materials and Effective K

机译:多孔低k材料和有效K

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By driving interconnect dimen-sions to ever-smaller sizes, the RC delay becomes the domi-nant factor to impact IC per-formance. The RC delay time is controlled by the re-sistance of the metal lines in the interconnect structure of an IC, and the capacitance between the metal lines. To reduce RC delay, copper interconnects were introduced to replace aluminum at the 175 nm generation for metal linewidths of 0.25 μm, utilizing copper's 37% lower resistivity than aluminum. The reduction of capacitance is still ongoing, and has happened in stages so far. SiO_2 (relative permeability k=4.1) was replaced by fluorinated silica (FSG, k=3.7) in the mid-90s. Currently, IC manufacturers are pushing the implementation of dense CVD SiCOH materials (k=2.7-3.0).
机译:通过将互连尺寸驱动到越来越小的尺寸,RC延迟成为影响IC性能的主要因素。 RC延迟时间由IC的互连结构中的金属线的电阻和金属线之间的电容控制。为了减少RC延迟,引入了铜互连,以取代175 nm的铝,金属线宽为0.25μm,铜的电阻率比铝低37%。电容的减少仍在进行中,到目前为止已经分阶段进行。在90年代中期,用氟化二氧化硅(FSG,k = 3.7)代替了SiO_2(相对磁导率k = 4.1)。当前,IC制造商正在推动采用致密CVD SiCOH材料(k = 2.7-3.0)。

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