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Modelling and Simulation of FinFET Circuits with Predictive Technology Models

机译:具有预测技术模型的FinFET电路的建模和仿真

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摘要

During analysis of complexities of the Metal Oxide Semiconductor Field Effect Transistors (MOSFET) technology to obtain the adequate gate control above the channel, FinFET technology founded on Double or Multiple gate (more than two gates) arrangement is improved technology alternative for auxiliary lessening the size of the MOSFET. In favor of double or dual gate MOSFET (DG MOSFET) the gate control above the channel that formed in between source and drain terminal efficiently. As a result the numerous short channel effects like sub-threshold swing, Drain Induced Barrier Lowering (DIBL-effect), gate leakage current, punch through etc. do not include growing of carrier concentration addicted to the channel. This paper is devoted to specific explanation on the subject of the DG MOSFET composition with its exacting kind termed the same as FinFET technology. FinFET technology has four modes such as shorted-gate (SG) mode, low power (LP) mode, independent-gate (IG) mode and hybrid IG/LP mode and performed the comparative analysis of stand-by leakage (when the circuit is idle), delay, total power consumption and noise of the circuit, using Cadence Virtuoso tool at 45 nm.
机译:在分析金属氧化物半导体场效应晶体管(MOSFET)技术的复杂性以在通道上方获得足够的栅极控制时,基于双栅极或多栅极(两个以上的栅极)布置的FinFET技术是改进的技术选择,可辅助减小尺寸MOSFET的。为了使用双栅极或双栅极MOSFET(DG MOSFET),栅极控制应有效地形成在源极和漏极端子之间的沟道上方。结果,许多短沟道效应,例如亚阈值摆幅,漏极诱导的势垒降低(DIBL效应),栅极泄漏电流,穿通等,都不包括沉迷于沟道的载流子浓度的增长。本文专门针对DG MOSFET组成的主题进行了专门的解释,其确切类型与FinFET技术相同。 FinFET技术具有四种模式,例如短栅(SG)模式,低功耗(LP)模式,独立栅(IG)模式和混合IG / LP模式,并进行了待机泄漏的比较分析(当电路处于使用Cadence Virtuoso工具在45 nm波长下的空闲,延迟,总功耗和电路噪声。

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