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Predicting parasitic capacitance in schematic circuit simulations using sub-circuit modeling
Predicting parasitic capacitance in schematic circuit simulations using sub-circuit modeling
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机译:使用子电路建模在原理图电路仿真中预测寄生电容
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摘要
A computer-implemented method of determining parasitic capacitance for transistors within an integrated circuit can include determining a first set of coefficients for a first expression that calculates parasitic capacitance for a transistor structure according to a first plurality of parasitic capacitances derived from a plurality of two-dimensional transistor structures (320). The first set of coefficients can be inserted into the first expression (325). The method further can include determining a second set of coefficients for a second expression that calculates parasitic capacitance for a transistor structure according to a second plurality of parasitic capacitances derived from a plurality of three-dimensional transistor structures (345). The second expression can include the first expression (350). The method can include inserting the second set of coefficients into the second expression and outputting the second expression (355).
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