Optimal Design of a High-Voltage DC/DC Converter for the 11.5-MW/115-kV ESS Long-Pulse Modulator

摘要

The stacked multilevel (SML) klystron modulator topology has been suggested as an alternative to conventional pulse transformer-based topologies in an attempt to improve output pulse performance and reduce system size for long-pulse applications. In this topology, a power converter chain including a high-frequency transformer generates the output pulse in a pulse modulation/demodulation scheme, eliminating the direct size-pulse length dependency inherently associated with pulse transformers while allowing a higher degree of freedom in design. This article details the design of the SML pulse generation stage with particular focus on the aspects of system extents volume, system efficiency, converter lifetime, and complexity. Key component design equations are derived and integrated into an optimal design routine used to primarily study trade-offs between volume and efficiency, as well as in selecting a design for ESS klystron modulator requirements-pulse amplitude 115 kV/100 A, pulse length 3.5 ms, pulse repetition rate 14 Hz, efficiency > 90%, and lifetime > 25 years. The chosen design is characterized through circuit simulation and 3-D finite element analysis, and is validated in power testing.