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Performance evaluation of high-speed interconnects using dense communication patterns

机译:使用密集通信模式的高速互连的性能评估

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We study the performance of high-speed interconnects using a set of communication micro-benchmarks. The goal is to identify certain limiting factors and bottlenecks with these interconnects. Our micro-benchmarks are based on dense communication patterns with different communicating partners and varying degrees of these partners. We tested our micro-benchmarks on five platforms: an IBM system of 68-node 16-way Power3, interconnected by a SP switch2; another IBM system of 264-node 4-way Power PC 604e, interconnected by an SP switch; a Compaq cluster of 128-node 4-way ES40/EV67 processor, interconnected by an Quadrics interconnect; an Intel cluster of 16-node dual-CPU Xeon, interconnected by an Quadrics interconnect; and a cluster of 22-node Sun Ultra Spare, interconnected by an Ethernet network. Our results show many limitations of these networks including the memory contention within a node as the number of communicating processors increased and the limitations of the network interface for communication between multiple processors of different nodes.
机译:我们使用一组通信微基准来研究高速互连的性能。目的是确定这些互连的某些限制因素和瓶颈。我们的微基准测试是基于与不同沟通伙伴以及这些伙伴不同程度的密集沟通模式。我们在五个平台上测试了微基准测试:一个由68个节点的16路Power3 IBM系统(通过SP交换机2互连);通过SP交换机互连的另一个264节点4路Power PC 604e IBM系统;由Quadrics互连互连的128节点4路ES40 / EV67处理器的Compaq集群;通过Quadrics互连互连的16节点双CPU Xeon英特尔集群;以及由以太网网络互连的22个节点的Sun Ultra Spare集群。我们的结果显示了这些网络的许多局限性,包括随着通信处理器数量的增加,节点内的内存争用以及不同节点的多个处理器之间进行通信的网络接口的局限性。

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