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MACS: A Highly Customizable Low-Latency Communication Architecture

机译:MACS:高度可定制的低延迟通信体系结构

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Networks-on-chips (NoCs) are an increasingly popular communication infrastructure in single chip VLSI design for enhancing parallelism and system scalability. Processing elements (PEs) connect to a communication topology via NoC switches, which are responsible for runtime establishment and management of inter-PE communication channels. Since NoC switch design directly affects overall system performance and exploited communication parallelism, much previous work focused on efficient NoC switch design. In this paper, we present MACS—a highly parametric NoC switch architecture that provides reduced data transfer latency, increased designer flexibility, and scalability as compared to previous architectures by combining and enhancing several NoC design strategies. MACS enhances inter-PE communication using a circuit switching technique with minimal adaptive routing and a simple and fair path resolution algorithm to maximize bandwidth utilization. We evaluate area and performance of an FPGA implementation of MACS, and, show that compared to previous work, MACS offers a 2x to 7x decrease in average channel setup latency, a 1.7x to 2x reduction in area requirements, similar average packet latency, up to a 6x increase in the network saturation point, and up to a 1.4x increase in bandwidth utilization. Additionally, we illustrate MACS’s low average channel setup latency using six network traffic patterns and eight parallel JPEG decompression core trace simulations.
机译:片上网络(NoC)是单芯片VLSI设计中日益流行的通信基础结构,用于增强并行性和系统可伸缩性。处理元件(PE)通过NoC开关连接到通信拓扑,该开关负责运行时建立和PE间通信通道的管理。由于NoC交换机设计直接影响整体系统性能并利用通信并行性,因此以前的许多工作都集中在有效的NoC交换机设计上。在本文中,我们介绍了MACS —一种高度参数化的NoC交换机体系结构,与以前的体系结构相比,通过组合和增强了几种NoC设计策略,可以降低数据传输延迟,提高设计灵活性和可扩展性。 MACS使用电路交换技术,最少的自适应路由和简单而公平的路径解析算法来最大程度地提高带宽利用率,从而增强了PE间通信。我们评估了MACS的FPGA实现的面积和性能,并表明与以前的工作相比,MACS的平均通道建立延迟减少了2到7倍,面积要求减少了1.7到2倍,平均数据包延迟也增加了网络饱和点提高了6倍,带宽利用率提高了1.4倍。此外,我们使用六个网络流量模式和八个并行JPEG解压缩核心跟踪仿真说明了MACS的低平均信道建立延迟。

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