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Performance analysis and structured parallelisation of the space-time adaptive processing computational kernel on multi-core architectures

机译:多核架构上时空自适应处理计算内核的性能分析和结构化并行化

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The development of radar systems on general-purpose off-the-shelf parallel hardware represents an effective means of providing efficient implementations with reasonable realisation costs. However, the fulfilment of the required real-time constraints poses serious problems of performance and efficiency: parallel architectures need to be exploited at best, providing scalable parallelisations able to reach the desired throughput and latency levels. In this paper we discuss the implementation issues of the computational kernel of a well-known radar filtering technique - the space-time adaptive processing - on today's general-purpose parallel architectures (multi-/many-core platforms). In order to address the performance constraints imposed by the realtime implementation of this filtering technique, we apply a structured approach (structured parallel programing) to develop parallel computations as instances and compositions of well-known parallelisation patterns. This paper provides a thorough description of the implementation issues and discusses the performance peaks achievable on a broad range of existing multi-core architectures.
机译:在通用的现成并行硬件上开发雷达系统代表了一种以合理的实现成本提供有效实施的有效手段。但是,满足所需的实时约束会带来严重的性能和效率问题:并行架构最多需要利用,提供可扩展的并行化能力,以达到所需的吞吐量和延迟水平。在本文中,我们讨论了在当今的通用并行体系结构(多核/多核平台)上,一种众所周知的雷达滤波技术的计算内核(时空自适应处理)的实现问题。为了解决此过滤技术的实时实施所施加的性能限制,我们应用结构化方法(结构化并行编程)来开发并行计算,作为实例和众所周知的并行化模式的组成。本文提供了有关实现问题的详尽描述,并讨论了在各种现有的多核体系结构上可达到的性能峰值。

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