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Centroiding algorithms for high speed crossed-strip readout of microchannel plate detectors

机译:用于微通道板检测器的高速交叉带读取的质心算法

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Imaging microchannel plate (MCP) detectors with cross-strip (XS) readout anodes require centroiding algorithms to determine the location of the amplified charge cloud from the incident radiation, be it photon or particle. We have developed a massively parallel XS readout electronic system that employs an amplifier and ADC for each strip and uses this digital data to calculate the centroid of each event in real time using a field programmable gate array (FPGA). Doing the calculations in real time in the front end electronics using an FPGA enables a much higher input event rate, nearly two orders of magnitude faster by avoiding the bandwidth limitations of the raw data transfer to a computer. We report on our detailed efforts to optimize the algorithms used on both 18 and 40 mm diameter XS MCP detector with strip pitch of 640 urn and readout with multiple 32 channel "Preshape32" ASIC amplifiers (developed at Rutherford Appleton Laboratory). Each strip electrode is continuously digitized to 12 bits at 50 MHz with all 64 digital channels (128 for the 40 mm detector) transferred to a Xilinx Virtex 5 FPGA. We describe how events are detected in the continuous data stream and then multiplexed into firmware modules that spatially and temporally filter and weight the input after applying offset and gain corrections. We will contrast a windowed "center of gravity" algorithm to a convolution with a special centroiding kernel in terms of resolution and distortion and show results with < 20 urn FWHM resolution at input rates > 1 MHz.
机译:具有交叉条(XS)读出阳极的成像微通道板(MCP)检测器需要质心算法,才能根据入射辐射(无论是光子还是粒子)确定放大后的电荷云的位置。我们已经开发出了大规模并行的XS读出电子系统,该系统在每个条带上都使用放大器和ADC,并使用此数字数据通过现场可编程门阵列(FPGA)实时计算每个事件的质心。通过使用FPGA在前端电子设备中实时进行计算,可以避免输入到计算机的原始数据的带宽限制,从而实现更高的输入事件发生率,快近两个数量级。我们报告了我们为优化18和40 mm直径XS MCP检测器所使用的算法所做的详细努力,该检测器的条带间距为640 um,并使用多个32通道“ Preshape32” ASIC放大器(在卢瑟福·阿普尔顿实验室开发)进行读出。每个条状电极均以50 MHz的频率连续数字化为12位,并将所有64个数字通道(对于40 mm检测器为128个)传输到Xilinx Virtex 5 FPGA。我们描述了如何在连续数据流中检测事件,然后将其复用到固件模块中,这些模块在应用偏移和增益校正后会在空间和时间上对输入进行过滤和加权。我们将在分辨率和失真方面将开窗的“重心”算法与具有特殊质心核的卷积进行对比,并在输入速率> 1 MHz时显示<20 um FWHM分辨率的结果。

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