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Software verification process and methodology for the development of FPGA-based engineered safety features system

机译:基于FPGA的工程安全特征系统开发的软件验证过程和方法

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摘要

Verification process is very important for the new development or re-engineering process for Instrumentation and Control (I&C) in Nuclear Power Plant (NPP). Due to the fact that the Engineered Safety Feature-Component Control System (ESF-CCS) is safety critical system, it is necessary to specify a systematic approach to verify the performance of development design. For this verification process, a system engineering approach is used and refers to the software design life cycle to verify the VHDL code in the implementation of Field Programmable Gate Array (FPGA)-based ESF-CCS. Although FPGA does not use software, however, FPGA needs a Hardware Description Language (HDL) to describe digital and mixed-signal for an integrated system. Therefore, the VHDL code should be verified to make sure that this code level will not cause an error for the FPGA-based system, especially for ESF-CCS development. The verification method is started by looking at the requirements analysis, verification of the outputs of the design by develop software testing to verify the reliability of the code which is to support the FPGA-based ESF-CCS. White Box testing is used for software testing to demonstrate the responds from the VHDL code, whether the design is success or not, and the coverage test is at 100% coverage state. In addition, the Static Timing Analysis (STA) is applied to check the delay time. Once all verification steps have been performed, then the results of the design can be validated. In this paper, FPGA-based ESF-CCS using VHDL code is verified.
机译:验证过程对于核电厂(NPP)的仪表与控制(I&C)的新开发或再工程过程非常重要。由于工程安全功能部件控制系统(ESF-CCS)是安全关键系统,因此有必要指定一种系统的方法来验证开发设计的性能。对于此验证过程,使用了一种系统工程方法,该方法指的是软件设计生命周期,以在基于现场可编程门阵列(FPGA)的ESF-CCS的实现中验证VHDL代码。尽管FPGA不使用软件,但是FPGA需要硬件描述语言(HDL)来描述集成系统的数字和混合信号。因此,应验证VHDL代码,以确保该代码级别不会对基于FPGA的系统(尤其是ESF-CCS开发)造成错误。验证方法从查看需求分析开始,通过开发软件测试来验证设计的输出,以验证代码的可靠性,该代码将支持基于FPGA的ESF-CCS。白盒测试用于软件测试,以演示来自VHDL代码的响应,设计是否成功以及覆盖率测试处于100%覆盖率状态。另外,应用静态时序分析(STA)来检查延迟时间。完成所有验证步骤后,即可验证设计结果。本文验证了使用VHDL代码的基于FPGA的ESF-CCS。

著录项

  • 来源
    《Nuclear Engineering and Design》 |2018年第4期|325-331|共7页
  • 作者单位

    KEPCO Int Nucl Grad Sch, KINGS Instrumentat & Control Lab, Dept Nucl Power Plant Engn, 658-91 Haemaji Ro, Ulsan 45014, South Korea;

    KEPCO Int Nucl Grad Sch, KINGS Instrumentat & Control Lab, Dept Nucl Power Plant Engn, 658-91 Haemaji Ro, Ulsan 45014, South Korea;

    KEPCO Int Nucl Grad Sch, KINGS Instrumentat & Control Lab, Dept Nucl Power Plant Engn, 658-91 Haemaji Ro, Ulsan 45014, South Korea;

  • 收录信息 美国《科学引文索引》(SCI);美国《工程索引》(EI);美国《生物学医学文摘》(MEDLINE);
  • 原文格式 PDF
  • 正文语种 eng
  • 中图分类
  • 关键词

    FPGA; Verification; ESF-CCS; IC;

    机译:FPGA;验证;ESF-CCS;I&C;

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