順序論理に基づくリコンフィギャラブルvlsiに関する研究

摘要

This article presents a reconfigurable VLSI for a bit-serial parallel processing based on a sequential logic operation. A universal sequential logic module (USLM) suitable for a sequential logic operation is presented. Direct allocation such that only a single node in a Data Flow Graph(DFG) is allocated to one cell composed of the multiple USLMs is introduced to make to reduce complexity of interconnection between multiple cells. A redundant multiple-valued sequential logic operation is also proposed, where linear summation of time-by-time adjacent bits is fully utilized to increase the input/output throughput of a sequential logic circuit. Moreover, packet data transfer scheme is introduced to make programmable interconnection between macro-operations constructed by using the multiple cells.%任意の演算回路を構成可能なリコンフィギャラブrnルVLSIはプログラマブルなロジック回路と配線スrnイッチからなるが，ロジック回路間に多数の配線スrnイッチが存在することで配線遅延が増加し，性能のrn低下要因となっている．