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A generic systolic array building block for neural networks with on-chip learning

机译:具有片上学习功能的神经网络的通用脉动阵列构建块

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Neural networks require VLSI implementations for on-board systems. Size and real-time considerations show that on-chip learning is necessary for a large range of applications. A flexible digital design is preferred here to more compact analog or optical realizations. As opposed to many current implementations, the two-dimensional systolic array system presented is an attempt to define a novel computer architecture inspired by neurobiology. It is composed of generic building blocks for basic operations rather than predefined neural models. A full custom VLSI design of a first prototype has demonstrated the efficacy of this design. A complete board dedicated to Hopfield's model has been designed using these building blocks. Beyond the very specific application presented, the underlying principles can be used for designing efficient hardware for most neural network models.
机译:神经网络要求车载系统采用VLSI。大小和实时性的考虑因素表明,片上学习对于许多应用来说都是必需的。在此,灵活的数字设计比更紧凑的模拟或光学实现更可取。与许多当前的实现相反,所提出的二维收缩阵列系统是试图定义一种受神经生物学启发的新型计算机体系结构。它由用于基本操作的通用构建块组成,而不是由预定义的神经模型组成。第一个原型的完整定制VLSI设计已经证明了该设计的有效性。使用这些构建块已经设计出了专用于Hopfield模型的完整电路板。除了给出的非常具体的应用之外,基本原理还可以用于为大多数神经网络模型设计有效的硬件。

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