An Adjacent-Line-Merging Writeback Scheme for STT-RAM-Based Last-Level Caches

摘要

Spin-Transfer Torque RAM (STT-RAM) has attracted attention as a key element for the Last-Level Cache (LLC) of a future microprocessor. Since STT-RAM has a higher density than SRAM and non-volatility, STT-RAM can contribute to building the cache memory wit