机译:使用Verilog HDL为基于内核的数字电路实现内置的自检环境
Department of Computer Science, College of Arts and Sciences, Troy University, Montgomery, AL 36103 USA,School of Information Technology and Engineering, Faculty of Engineering, University ofOttawa, Ottawa, ON KIN 6N5, Canada;
School of Information Technology and Engineering, Faculty of Engineering, University ofOttawa, Ottawa, ON KIN 6N5, Canada;
School of Engineering and Physics, Faculty of Science and Technology, University of the South Pacific, Suva, Fiji;
School of Engineering and Computer Science, Independent University, Dhaka 1329, Bangladesh;
School of Information Technology and Engineering, Faculty of Engineering, University ofOttawa, Ottawa, ON KIN 6N5, Canada;
built-in self-test (BIST); embedded cores-based systems; module under test (MUT); response compaction unit (RCU);
机译:一种新颖的双重状态跳跃逻辑内置数字电路自测方案
机译:用于数字电路单事件测试的内置自测(BIST)技术
机译:用于数字低压丢失稳压器的泄漏感知垂直测量内置自检电路
机译:基于Verilog HDL的浮点算法在人工神经网络中数字逻辑电路的实现
机译:在Altera MAX Plus II开发环境下,使用Verilog HDL测试基于嵌入式内核的时序电路的实现。
机译:具有数字内置自检功能的MEMS加速度计的ΣΔ闭环接口
机译:用于高性能自动增益控制电路的数字部分内置自测结构
机译:模拟电路的混合信号内置自检