A Ultra-High PAE Doherty Amplifier Basedon 0.13-$mu$m CMOS Process

摘要

A 2.4-GHz Doherty CMOS power amplifier (PA) with ultra-high efficiency [power added efficiency (PAE)] is presented. A 0.13-$mu$m standard CMOS process is employed and the two-stage circuit is configured for a 3.2-V operation. For a compact realization of the circuit, all matching circuits including a quarter wave transformer and input phase compensation transmission lines are implemented with lumped components. To modulate properly and maximize the PAE at$P_1 dB$, the input power of the class C peaking power cell is adjusted by optimizing the gate bias of the peaking driver cell. By doing so, the gain compression of the carrier cell is compensated by the gain expansion of the peaking cell up to the full power. This amplifier delivers a 22.7dBm of$P_1 dB$and 60% of PAE with 25dB of power gain at 2.4 GHz. The PAE at 5 dB backed-off power level shows about 35%. The excellent PAE of the circuit is the best data ever reported from linear CMOS PAs. The successful demonstration of the Doherty CMOS PA with lumped components is expected to be applied for a full-integration of the circuit.