首页> 外文期刊>Microwave and Wireless Components Letters, IEEE >A 16 Path All-Passive Harmonic Rejection Mixer With Watt-Level In-Band IIP3 in 45-nm CMOS SOI
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A 16 Path All-Passive Harmonic Rejection Mixer With Watt-Level In-Band IIP3 in 45-nm CMOS SOI

机译:16条路径全无源谐波抑制混频器,具有45nm CMOS SOI中的瓦特级内IIP3

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This work presents an all-passive harmonic rejection mixer (HRM) with watt-level in-band IIP3. The HRM operates in the voltage mode using resistors to scale the voltages of the different paths across the frequency cycle and therefore, attains very high linearity. The passive HRM employs a non-overlapping clock generation chain combined with duty cycle control circuit to trim the rise and fall times of the individual paths, and maintains the harmonic rejection ratio (HRR) over the frequency band. Two 0.13–3 GHz 16-path HRM chips are fabricated in 45-nm CMOS silicon-on-insulator (SOI) technology using thin and thick-oxide devices, respectively, with 80-MHz IF bandwidth and a core area 0.06 mm2. The thick-oxide HRM achieves a HRR >35 dBc for all harmonics up to 3 GHz with a conversion loss of 8–10 dB, while the in-band IIP3 is 24–31 dBm and IP1 dB is 11–13 dBm for an RF of 0.5–3 GHz. To the authors knowledge, the all-passive 16-path HRM achieves the highest reported in-band IIP3 and IP1 dB.
机译:这项工作介绍了一种带有WATT级内IIP的全动谐波抑制混合器(HRM) 3 。 HRM使用电阻在电压模式下操作,以缩放频率周期的不同路径的电压,因此,达到非常高的线性。无源HRM采用非重叠的时钟生成链与占空比控制电路组合以修剪各个路径的上升和下降时间,并在频带上保持谐波抑制比(HRR)。使用薄和厚氧化物器件,在45-Nm CMOS硅 - 绝缘体(SOI)技术中,使用薄氧化物和厚氧化物器件,使用80-MHz,如果带宽和0.06 mm的核心区域 2 。厚氧化物HRM为高达3 GHz的HRR> 35 dBc,转换损耗为8-10 dB,而带内IIP 3 是24-31 dBm和IP 1 db 对于0.5-3 GHz的RF为11-13 dBm。对于作者的知识,全部被动的16-PATH HRM实现了最高报告的带内IIP 3 和IP. 1 db

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