Executing large algorithms on low-capacity FPGAs using flowpath partitioning and runtime reconfiguration

摘要

This paper describes a new method of executing a software program on an FPGA for embedded systems. Rather than combine recon-figurable logic with a microprocessor core, this method uses a new technique to compile Java programs directly to special-purpose processors that are called "flowpaths". Flowpaths allow a software program to be executed in such a way that one low-capacity FPGA is executing a piece of the program while a second low-capacity FPGA is being dynamically reconfigured to take over execution after the first one has completed its task. In this fashion, the program is executed by continuously alternating between the two chips. This process allows large programs to be implemented on limited hardware resources and at higher clock frequencies on an FPGA. The sequencer and rules for partitioning a flowpath are presented and the method is illustrated using a genetic algorithm compiled from Java directly to flowpaths using a flowpath compiler designed in our lab. The genetic algorithm flowpath requires 68% of an expensive, high-density Virtex2 XC2V8000 with a maximum frequency of 68.9 MHz (this genetic algorithm would have required 285% of the smaller, more reasonably priced Virtex 1000). However, by splitting flowpaths as presented in this paper, the algorithm can be implemented with an average maximum clock frequency of 154.8 MHz using only two low-capacity, inexpensive Virtex XCV50 chips, the smallest capacity of the Virtex family. The split flowpaths require one-quarter of the clock cycles used by the JStamp microcontroller. Therefore, instead of using an expensive high-density FPGA, the proposed design illustrates how a genetic algorithm can be implemented using only a pair of inexpensive chips that have only 50,000 equivalent gates each; a low-cost sequencer; and 11.81 MB of memory to store bit files. The overall time performance depends on the speed of the FPGA reconfiguration process.