首页> 外文期刊>Microprocessors and microsystems >The ACROSS MPSoC - A new generation of multi-core processors designed for safety-critical embedded systems
【24h】

The ACROSS MPSoC - A new generation of multi-core processors designed for safety-critical embedded systems

机译:ACROSS MPSoC-专为安全关键型嵌入式系统设计的新一代多核处理器

获取原文
获取原文并翻译 | 示例
           

摘要

The European ARTEMIS ACROSS project aims to overcome the limitations of existing Multi-Processor Systems-on-a-Chip(MPSoC)architectures with respect to safety-critical applications. MPSoCs have a tremendous potential in the domain of embedded systems considering their enormous computational capacity and energy efficiency. However, the currently existing MPSoC architectures have significant limitations with respect to safety-critical applications. These limitations include difficulties in the certification process due to the high complexity of MPSoCs, the lacking temporal determinism and problems related to error propagation between subsystems. These limitations become even more severe, when subsystems of different criticality levels have to be integrated on the same computational platform. Examples of such mixed-criticality integration are found in the avionics and automotive industry with their desire to integrate safety-critical, mission critical and non-critical subsystems on the same platform in order to minimize size, weight, power and cost. The main objective of ACROSS is to develop a new generation of multi-core processors designed specially for safety-critical embedded systems; the ACROSS MPSoC. In this paper we will show how the ACROSS MPSoC overcomes the limitations of existing MPSoC architectures in order to make the multi-core technology available to the safety-critical domain. The proposed approach enables efficient certification, complexity management, mixed-criticality integration and the development of temporally deterministic hard real-time systems. The major technological innovations of ACROSS are an increased level of design abstraction, message-based interfaces for core-to-core communication and reliable fault and error containment established by a novel time-triggered net-work-on-chip. The achieved results comprise, a novel architecture for MPSoCs, a prototype implemena-tion on FPGA technology as a proof-of-concept, a comprehensive set of middle-ware services and multiple demonstrators that show the benefits of the ACROSS Architecture in real world industrial applications.
机译:欧洲ARTEMIS ACROSS项目旨在克服现有的多处理器片上系统(MPSoC)体系结构在安全性关键应用方面的局限性。考虑到MPSoC的巨大计算能力和能效,它们在嵌入式系统领域具有巨大潜力。但是,当前存在的MPSoC架构在安全性至关重要的应用方面存在很大的局限性。这些限制包括由于MPSoC的高度复杂性,缺乏时间确定性以及与子系统之间的错误传播相关的问题而导致的认证过程中的困难。当必须将不同关键级别的子系统集成到同一计算平台上时,这些限制将变得更加严峻。在航空电子和汽车工业中发现了这种混合临界集成的示例,它们希望将安全关键,任务关键和非关键子系统集成在同一平台上,以最大程度地减小尺寸,重量,功率和成本。 ACROSS的主要目标是开发专门为安全关键型嵌入式系统设计的新一代多核处理器。 ACROSS MPSoC。在本文中,我们将展示ACROSS MPSoC如何克服现有MPSoC架构的局限性,从而使多核技术可用于安全关键领域。所提出的方法能够进行有效的认证,复杂性管理,混合关键度集成以及时间确定性硬实时系统的开发。 ACROSS的主要技术创新是设计抽象水平的提高,用于核心对核心通信的基于消息的接口以及由新型的时间触发芯片网络建立的可靠的故障和错误遏制能力。所取得的成果包括用于MPSoC的新颖架构,作为概念验证的FPGA技术原型实现,全套中间件服务以及多个演示器,它们展示了ACROSS架构在现实世界工业中的优势。应用程序。

著录项

相似文献

  • 外文文献
  • 中文文献
  • 专利
获取原文

客服邮箱:kefu@zhangqiaokeyan.com

京公网安备:11010802029741号 ICP备案号:京ICP备15016152号-6 六维联合信息科技 (北京) 有限公司©版权所有
  • 客服微信

  • 服务号