HMMC: A memory controller for heterogeneous Multi-core System

摘要

In a multi-core environment, the memory system and the scheduling of memory accesses are important factors that influence the performance of applications. The system n encounters multiple delays (e.g. memory and task management), which degrade the overall system performance. This performance degradation demands an efficient memory system and high speed scheduler, which feeds complex data access patterns to the appropriate processing core. In this work, we propose an efficient scheduler and intelligent memory manager for heterogeneous Multi-core System, known as HMMC (Heterogeneous Multi-Core Memory Controller), which proficiently handles data movement and computational tasks. The proposed HMMC system improves performance by managing complex data transfers at run-time and scheduling multi-cores without the intervention of a control processor or an operating system. HMMC has been coupled with a heterogeneous system that provides both general-purpose cores and application specific accelerators. The HMMC system is implemented and tested on a Xilinx XC7VX485T FPGA VC707 evaluation board. In order to prove that our controller is efficient in a variety of scenarios, we run 17 benchmarks concurrently containing with different scheduling policies. The performance of the system is compared with a microprocessor based system that has been integrated with the Xilkernel operating system. Results show that the HMMC based heterogeneous multi-core system consumes 43% less hardware resources, 35.8% less dynamic power and achieves 6.8x of speed-up compared to the MicroBlaze-based heterogeneous multi-core system having Xilkernel support. (C) 2015 Elsevier B.V. All rights reserved.